Semiconductor memory devices require high productivity and high quality to obtain market competitiveness. Consequently, methods for improving product quality and productivity are continuously being developed. One proposed method for improving the quality of the semiconductor memory device is analyzing a wafer to determine causes of problems at the wafer level.
A variety of data on semiconductor products are generally stored at the wafer level as “package map data”. More specifically, package map data such as a production date and position data in the wafer are stored at the wafer level by using fuse elements, thereby enabling easy analysis of the data at the package level. The stored package map data is generally output through an input pad in the semiconductor device. The number of input pads to be exposed at the package level for a given product is fixed. Thus, it is very difficult to additionally assign a large amount of package pins to output the package map data stored in the semiconductor memory chip. Indeed, because of the difficulty in arranging package pins, it is preferable to minimize the number of package pins that are not related to operation of the semiconductor memory.
FIG. 1 is a conventional circuit for storing and outputting package map data. Referring to FIG. 1, a plurality of N-type MOS transistors N1–N6 are connected in series between a power pin POWER1 and a pad PAD1, and a plurality of fuses F1–F4 are connected to node N01. With the circuit of FIG. 1, it is possible to input data for the following 5 cases: no fuses are cut; the fuse F1 is cut; the fuses F1, F2 are cut; the fuses F1, F2, F3 are cut; or the fuses F1, F2, F3, F4 are cut. That is, data can be input to the pad PAD1 with either of the aforementioned 5 different cases. As a result, if the number of input pads are n (where, n is an integer), it is possible to store n squares of 5 data.
Operations of the circuit shown in FIG. 1 is described below. During a normal operation mode, electric current does not flow because the voltage level of the power pin POWER1 is higher than that of the pad PAD1. During a test operation mode for checking the data stored (via the cutting fuses), 0 volt is applied to the power pin POWER1 and voltage is applied to the pad PAD1, which voltage is greater than the number of transistors multiplied by threshold voltage. Then, depending on which fuses were cut, a given amount of electric current will flow depending on the number of transistors connected in series. Therefore, it is possible to check the stored package map data by measuring the amount of electric current. At this time, the levels of electric current flowing in each of the transistors is different because of, e.g., differences in transistor characteristic depending on voltages and temperature. Therefore, even if various package products have the same map data, because of differences in the current, the stored data may be incorrectly decoded.
As described above, conventional analog methods for decoding the package map data can result in erroneous data interpretation. Further, conventional methods do not allow a large amount of data to be stored through corresponding pads when the package map data are stored at the wafer level. Moreover, it has proven to be difficult to interpret data when the data is stored by using tetrad data or more data.